The present invention relates to a semiconductor device including a memory cell that needs to be refreshed for storing data therein.
Typically, a DRAM requires a refresh operation. There is a refresh control method for a DRAM in which a control signal is provided externally, whereby a refresh address is generated by an internal counter, or the like. A refresh control method of this type is called xe2x80x9cauto refreshxe2x80x9d. While an auto refresh operation is being performed, a normal read or write operation cannot be performed.
A DRAM that operates in synchronism with a clock is described in, for example, Japanese Laid-Open Patent Publication No. 2000-163966. In such a DRAM, circuits of the row system operate based on a first edge of a clock, and circuits of the column system operate based on a second edge of the clock.
FIG. 14 illustrates an example of a DRAM that has an auto refresh function and operates in synchronism with a clock. In the figure, CLK denotes a clock, NRAUT denotes an auto refresh control signal, NRAS denotes a row control signal, and NCAS denotes a column control signal. The general operation of the DRAM will now be described with reference to a timing diagram of FIG. 15. Upon activation (transition to an L level) of the auto refresh control signal NRAUT in synchronism with the second leading edge of the clock from the left side, an auto refresh operation is performed. It is assumed in this example that an auto refresh operation requires two clocks. The auto refresh operation finishes at the fourth leading edge of the clock from the left side, after which a read operation, for example, can be performed. In this example, a read operation is completed in two clocks by activating (bringing to the L level) the control signal NRAS at the fourth leading edge of the clock from the left side, and activating (bringing to the L level) the control signal NCAS at the fifth leading edge of the clock from the left side. In the illustrated example, the next auto refresh operation can be performed from the sixth leading edge of the clock.
As described above, in a conventional DRAM, a refresh operation and a normal read/write operation are performed as separate operation cycles, whereby it is necessary to insert a cycle for a refresh operation while holding a read/write operation for every predetermined refresh period, thereby lowering the data transfer rate of the DRAM. Particularly, when the predetermined refresh period is short, it is necessary to insert a refresh operation cycle frequently, thereby significantly lowering the data transfer rate.
An object of the present invention is to provide a semiconductor device such as a DRAM that requires a refresh operation in which the reduction in data transfer rate due to the refresh operation is suppressed or prevented so as to achieve a higher data transfer rate than in the prior art.
In order to achieve the object, the present invention employs a configuration such that when a data read or write operation is requested, a single refresh operation can be automatically performed within the data read or write cycle, and when a data read or write operation is not requested, each auto refresh operation can be completed within a single clock.
Specifically, a semiconductor device of the present invention includes: a plurality of memory cells that need to be refreshed for storing data therein; a plurality of sense amplifiers for amplifying data read out from the memory cells; and a refresh control signal generation circuit for, when a data read or write operation is requested, generating a refresh control signal upon receiving a data read or write control signal, wherein each refresh operation is performed within a single read or write operation cycle.
In one embodiment of the present invention, the refresh control signal generation circuit instructs the sense amplifiers to start operating and perform a refresh operation before the data read or write operation based on the refresh control signal.
In one embodiment of the present invention, the refresh control signal generation circuit activates a row selection control signal for a refresh operation as the refresh control signal upon receiving a row selection control signal as the data read or write control signal.
In one embodiment of the present invention, the semiconductor device further includes: a sense state signal generation circuit for generating a sense state signal according to a data amplification operation by the sense amplifiers; and a row selection control circuit for inactivating the refresh control signal of the refresh control signal generation circuit based on the sense state signal of the sense state signal generation circuit after initiation of a refresh operation by the refresh control signal generation circuit, and for re-initiating an operation of the sense amplifiers by generating a row selection control signal for a normal operation as the data read or write control signal after completion of an operation of the sense amplifiers.
In one embodiment of the present invention, the sense state signal generation circuit generates, as the sense state signal, a sense activation completion signal that indicates completion of activation of the sense amplifiers.
In one embodiment of the present invention, the row selection control circuit generates an amplification completion signal obtained by delaying the sense activation completion signal of the sense state signal generation circuit by an amount of time equal to or greater than an amount of time that is required from activation of the sense amplifiers until data on a bit line is sufficiently amplified, and inactivates the refresh control signal and activates the row selection control signal for a normal operation based on the amplification completion signal.
In one embodiment of the present invention, the row selection control circuit includes: a refresh counter; an address latch for latching a row address of data to be read or written; an address selection circuit; and a selection control circuit for instructing the address selection circuit to select a row address latch side after completion of an operation of the sense amplifiers based on a sense activation completion signal of the sense state signal generation circuit.
In one embodiment of the present invention, the semiconductor device further includes a refresh address updater for updating the refresh counter by generating a refresh count signal immediately after the address selection circuit selects the row address latch side according to the instruction from the selection control circuit.
In one embodiment of the present invention, the semiconductor device further includes: a column selection control circuit for outputting a column selection control signal and reading or writing data that has been amplified by the sense amplifiers based on the row selection control circuit; and a reset circuit for terminating an operation of the sense amplifiers by inactivating the row selection control signal for a normal operation of the row selection control circuit after completion of the data read or write operation by the column selection control circuit.
In one embodiment of the present invention, the semiconductor device further includes an internal auto refresh control signal generation circuit for generating an internal auto refresh control signal upon receiving an auto refresh control signal when a data read or write operation is not requested, wherein the refresh operation is performed through a single refresh operation that is performed within a single read or write operation cycle and an auto refresh operation that is performed when there is no read or write operation to be performed.
In one embodiment of the present invention, the auto refresh control signal is input to the refresh control signal generation circuit, and the internal auto refresh control signal is generated by the refresh control signal generation circuit, which functions also as the internal auto refresh control signal generation circuit.
In one embodiment of the present invention, the semiconductor device further includes a reset circuit for, when the internal auto refresh control signal is generated, stopping the generation of the row selection control signal for a normal operation by the row selection control circuit.
In one embodiment of the present invention, the semiconductor device further includes: a refresh counter; an address latch for latching a row address of data to be read or written; an address selection circuit; a selection control circuit for instructing the address selection circuit to select a row address latch side after completion of an operation of the sense amplifiers based on a sense activation completion signal of the sense state signal generation circuit; and a refresh address updater for updating the refresh counter by generating a refresh count signal immediately after the address selection circuit selects the row address latch side according to the instruction from the selection control circuit, wherein the refresh counter, the address latch, the address selection circuit, the selection control circuit and the refresh address updater are shared by a refresh operation that is performed within a single read or write operation cycle and an auto refresh operation that is performed when the read or write operation is not being performed.
In one embodiment of the present invention, the semiconductor device further includes: a fuse circuit for replacing a word line having a defective memory cell connected thereto by a spare word line and for storing an inoperable row address; and a fuse reset circuit for resetting the inoperable row address of the fuse circuit each time a data read or write operation based on the column selection control circuit is completed.
In one embodiment of the present invention, the semiconductor device further includes a reset circuit for, when the column selection control signal from the column selection control circuit is not activated at a predetermined clock edge, resetting the row selection control signal for a normal operation from the row selection control circuit after passage of a predetermined amount of time from the predetermined clock edge.
In one embodiment of the present invention, the refresh control signal generation circuit dose not activate the row selection control signal for a refresh operation as the refresh control signal when the row selection control signal as the data read or write control signal is received consecutively at leading or trailing edges of a clock.
Another semiconductor device of the present invention includes: a plurality of memory cells that need to be refreshed for storing data therein; a plurality of sense amplifiers for amplifying data read out from the memory cells; an internal auto refresh control signal generation circuit for, when a data read or write operation is not requested, generating an internal auto refresh control signal upon receiving an auto refresh control signal; a sense state signal generation circuit for generating a sense state signal according to a data amplification operation by the sense amplifiers; and a row selection control circuit for inactivating the refresh control signal of the internal auto refresh control signal generation circuit based on the sense state signal of the sense state signal generation circuit after initiation of an auto refresh operation by the internal auto refresh control signal generation circuit, wherein each auto refresh operation is performed within a single clock.
Thus, according to the present invention, when a data read or write operation is requested, the refresh control signal generation circuit generates a refresh control signal. Therefore, for every data read or write operation cycle, a refresh operation based on the refresh control signal is performed within the operation cycle. As a result, it is no longer necessary to perform an auto refresh operation for every refresh period, thereby increasing the data transfer rate of the semiconductor device.
According to the present invention, when a data read or write operation is requested, a refresh operation is performed first, and the data read or write operation is performed following the completion of the refresh operation. Particularly, the row address (external row address) of data to be read or written that has been latched by the row address latch is selected by the address selection circuit based on the sense activation completion signal generated in the refresh operation, which is performed first. Therefore, when initiating the data read or write operation, which is to be performed later, decoding of the external row address is already completed, thereby reducing the read or write cycle by the amount of time saved.
Moreover, according to the present invention, the refresh counter is selected immediately after the address selection circuit selects the row address latch. Therefore, when the next data read or write operation is requested, decoding of the refresh address in the refresh operation, which is performed first, is completed, thereby further reducing the data read or write cycle by the amount of time saved.
Furthermore, according to the present invention, after the column selection operation in the read or write operation is completed, the data read or write control signal is inactivated with the operation of the sense amplifiers being terminated, and the bit line through which data from memory cells is to be read out is precharged. Thus, it is possible to perform a column control, stop the operation of sense amplifiers and to precharge a bit line within a single clock, thereby reducing the number of clock cycles for a data read or write operation.
Furthermore, according to the present invention, an auto refresh operation is performed based on the auto refresh control signal when a data read or write operation is not requested. Particularly, the auto refresh control signal generation circuit, the refresh counter, etc., are shared, whereby it is possible to reduce the number of circuits and the actual evaluation of these circuits is simplified.
In addition, according to the present invention, even if the programmed value (inoperable address) stored in the fuse circuit changes due to an influence of noise, or the like, the programmed value is reset for every read or write cycle, thereby preventing erroneous replace.
Moreover, according to the present invention, even in a dummy cycle or in a case where the column selection control signal is erroneously in an inactive state at a predetermined clock edge, the active state of the data read or write control signal of the row selection control circuit can be maintained for a relatively long period of time, and the sense amplifier operation can be maintained for an accordingly extended period of time, thereby preventing malfunction of the semiconductor device.
Furthermore, according to the present invention, in a page operation mode in which the row selection control signal is consecutively received over more than one clock cycles, the row selection control signal for a refresh operation is not activated for the second and subsequent clock cycles, whereby data can be immediately read or written without performing the refresh operation.
In addition, according to the present invention, the sense state signal generation circuit generates the sense state signal according to the data amplification operation by the sense amplifiers. Therefore, after the internal auto refresh control signal generation circuit generates the internal auto refresh control signal based on a leading edge of the clock, thereby initiating the internal auto refresh operation, the generation of the internal auto refresh control signal is stopped upon completion of the data amplification operation, which is determined based on the sense state signal. Therefore, it is possible to complete the auto refresh operation within a single clock.